Due to continued advances in CMOS technology, the number of devices integrated on a single chip keeps increasing at a rapid rate with each generation. Recent progress in 3D stacking using through-silicon vias (TSVs) as well as decreasing feature size has enabled even denser integration in a single package. Today's complex System-on-Chips (SoCs) also integrate a large number of digital-logic components besides microprocessors, for instance, audio and video encoders, graphic cores, and various I/O controllers. All these components, including the glue logic, need to be tested efficiently to manage test cost. However, in order to test such complex chips, a large number of test vectors are required, thereby resulting in high test-data volume and test time. Test-data compression is now widely used to reduce test-data volume and test time, and overcome tester limitations related to memory, data transfer rates, and pin counts.
There continues to be the need for even more effective test-data compression and efficient test-application methods in order to manage escalating test cost. Fortunately, ICs have the potential to integrate a large amount of fast memory with high bandwidth and low access time in a single package, opening up new opportunities for using on-chip resources for test application.